1. Field of the Invention
The present invention relates to the field of digital comparators, and more specifically to a digital comparator using a carry lookahead adder.
2. Discussion of the Related Art
Many electronic circuits use numerical calculation circuits enabling in particular to compare two numbers A and B having the same number of bits.
FIG. 1 very schematically shows the structure of a conventional complete comparator, providing an indication of equality, superiority A greater than B, or inferiority A less than B.
A first block 11 receives on a first input an operand A, on a second input an operand B, and generates an output signal indicating whether A=B. A second block 12 receives on two inputs operands A and B, performs operation Axe2x88x92B and generates two outputs, one corresponding to A less than B, and the other corresponding to Axe2x89xa7B. Logic elements 13, 14 receiving the signals corresponding to Axe2x89xa7B and A=B determine whether A=B or whether A greater than B. With operation Axe2x88x92B corresponding, in binary coding, to operation A+{overscore (B)}+1, block 11 is conventionally an adder adding A, {overscore (B)}, and an incoming carry equal to 1.
In the following description, Ai and Bi will designate the n bits of operands A and B, i being included between 1 and n.
FIG. 2 shows an example of structure of block 11 of FIG. 1. An X-OR gate 21 receives on a first input bit A1 of the first operand A and on a second input bit B1 of the second operand B. The output of X-OR gate 21 will be at a high logic level xe2x80x9c1xe2x80x9d in case of an equality between bits A1 and B1xc2x7n X-OR gates 21 thus enable determining, rank by rank, the equality or the inequality of the bits of same rank of the first and second operands. The outputs of these X-OR gates are connected to the n inputs of an AND gate 22. The output of AND gate 22 will be at a high logic level xe2x80x9c1xe2x80x9d in case of a bit to bit equality of the first and second operands.
An object of the present invention is to provide a complete comparator using a reduced number of logic gates.
This objects as well as others is achieved by a digital comparator which includes a first block receiving on first inputs the bits of a first operand A of n bits and on second inputs the logic complements of the bits of a second operand B of n bits, generating a propagation signal             p      n        =                            π                      i            =            1                    n                ⁢                              P            i                    ⁢                      xe2x80x83                    ⁢          where          ⁢                      xe2x80x83                    ⁢                      P            i                              =                        A          i                +                              B            _                    i                      ,
and a generation signal             g      n        =                                        ∑                          i              =              1                                      n              -              1                                ⁢                      (                                          G                i                            ⁢                              π                                  j                  =                                      i                    +                    1                                                  n                            ⁢                              P                j                                      )                          +                              G            n                    ⁢                      xe2x80x83                    ⁢          where          ⁢                      xe2x80x83                    ⁢                      G            i                              =                        A          i                ·                              B            _                    i                      ,      xe2x80x83    ⁢            g      1        =          G      1        ,
which includes a second block receiving on a first input the most significant bit An of the first operand, on a second input the logic complement {overscore (B)}n of the most significant bit Bn of the second operand, on a third input propagation signal Pn, on a fourth input generation signal gn, generating signals Cn and Sn+1 such that Cn=pn+gn and Sn+1=(pn+gn)⊕An⊕{overscore (B)}n, where sign ⊕ represents operation X-OR, and which also includes a third block receiving on a first input signal pn and on a second input signal gn, and generating a signal E such that E=pnxc2x7{overscore (g)}n, indicating by a predetermined state that operands A and B are equal.
According to another aspect of the present invention, the first and second blocks both belong to a carry lookahead adder, the first block belonging to a block of the adder used to calculate all propagation signals pi and all generation signals gi, where i is included between 1 and n, and the second block belonging to a block of the adder used to calculate all sum signals Si, where i is included between 1 and n+1, and outgoing carry signal Cn, an incoming carry signal of the second block being set to 1.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.